1. Field of the Invention
This invention relates to a method and system for optimizing the creation, utilization, and characterization of standard cells used in the design of integrated circuits, that are particularly suitable for design-specific standard cells.
2. Description of the Related Art
Integrated circuits (ICs) form the heart of electronic engineering technology. The design and fabrication processes of ICs are extremely complex. Numerous methodologies, based on various technologies and tools, are known for accomplishing the design and fabrication of ICs. Prominent IC design methodologies include custom, semi-custom, gate-array, standard-cell, FPGA (field-programmable gate arrays).
It is generally accepted that standard cell based solutions provide an acceptable balance in terms of cost and performance for the implementation of ASICs (application specific integrated circuits), as well as several other forms of ICs. A typical standard-cell based design is implemented using a specific set of predefined logic cells referred to as standard-cells. The set of standard-cells is typically referred to as a library. Each (unique) standard cell is typically instantiated multiple times and the IC design is realized by the creation of appropriate interconnections between the instantiations.
Popular methods for implementing a standard cell based IC design use a fixed library of standard-cells for multiple designs. While a typical state-of-the-art standard-cell library may contain as many as several hundred to a thousand or more cells, IC design synthesis tools tend to use a small subset of the available cellsxe2x80x94typically in the range of 80-200 unique cells. Consequently, there is a great need to efficiently identify the cells in a given library that may be able to provide a better implementation of the functionality of a design, as measured using commonly used metrics such as performance or area.
More recently, digital IC design methodologies have been developed that utilize on-the-fly generation of standard cells as disclosed in commonly assigned U.S. patent Ser. No. 09/896,071, now U.S. patent application Publication Ser. No. 20020053063, entitled Process for Automated Generation of Design-Specific Complex Functional Blocks to Improve Quality of Synthesized Digital Integrated Circuits in CMOS, and incorporated herein by reference. In order to improve the efficiency of such design methodologies, there exists the need to (1) reduce the number of unique cells required to implement the design (Uniquification); and (2) efficiently characterize the properties of newly implemented cells (Characterization).
A primary focus in conventional, automated, design methodologies is placed on effective technology mapping. That is, the process of mapping the design to an existing technology-dependent library of standard-cells. The most important step in the mapping process is that of matching a target functional description with the functionality of a physical implementation (e.g., a standard-cell). For example, consider the example of FIG. 1. The target function f=(xy+zy)xe2x80x2 can be implemented by available AOI cell 105 in the library whose functionality is given by f=(a(b+c))xe2x80x2. However, in order to achieve this implementation, the inputs of the target function would need to be permutated in a certain order. In this example, two such permutations can result in an implementation of the target function with AOI cell 105. The two permutations that can result in a match in functionality are (a:y, b:x, c:z) and (a:y, b:z, c:x), as shown in the table of FIG. 1a. 
It should also be noted that a function f=(xy+zxe2x80x2y)xe2x80x2 can also be realized by the same AOI cell 105, if inverters were permitted to be used freely in the mapping process. Both of the permutations introduced above would still be valid, except that an inverter is required at the input of the AOI cell that matches the z input of the target cell in order to realize the correct target function. For example, in the permutation (a:y, b:x, c:z), the input c requires an inverter in order to realize the target function.
The technology mapping problem is well-known in conventional logic synthesis, it belongs to the category of computationally difficult problems designated as NP-hard. The problem is hard because of the necessity to consider exhaustive input permutations in order to realize potential matches, and the number of possible input permutations grows exponentially with the number of inputs. It is also known that the problem becomes much harder if input complementation is allowed in addition to permutation during the mapping process.
Previous work related to the uniquification problem has primarily addressed the issue of efficient matching of target functionality with the pre-existing library of standard-cells after considering potential permutations and complementation of inputs.
Present techniques to solve this matching problem use functional signatures to eliminate the necessity for the exhaustive generation of permutations and to limit the search space to a manageable size. Functional signatures capture essential properties of a given function (or library cell) that remain invariant even under input permutations/complementation. For example, the size of the ON-set of a function remains invariant under a permutation of input variables. Several other types of functional signatures are also known.
There also exists related work in the area of functional verification that attempts to match portions of a digital circuit (specification) with portions of another digital circuit (implementation) with an objective of comparing their functional equivalences. Techniques used in this area rely on both structural and functional information in order to identify similar portions of the specification and the implementation. In contrast with technology mapping techniques, functional verification techniques can use structural information since the structural views for both the implementation and the specification are known and available.
Characterization refers to the process by which standard cells designed for use in digital ICs designs are extensively analyzed for a number of characteristics such as, but not limited to, timing, power, area, noise, slew, load capacitance, drive strength, and footprint (i.e., size).
Most of the previous work in the area of characterization has focused on methods for reducing simulation times required for characterization. The methods used were typically based on improved models of the underlying devices and better numerical solution methods to solve the mathematical equations formed by modeling the underlying devices.
Prior work on improving the characterization accuracy of the design primarily concentrated on either (1) improving the gate-level timing analysis by considering such issues as false-paths or (2) by performing a characterization of the entire design at the transistor-level for a small set of all possible inputs (since it is not computationally feasible to completely characterize large designs at the transistor-level).
Much of the previous work related to characterization has focused on reducing the time required for extensive circuit simulation. A major disadvantage of previous efforts in the area of characterization is the assumption that the cells are typically designed and characterized without an idea of their potential points of instantiation in any design.
The present invention discloses methods for effectively solving all of the problems mentioned above for both traditional design methodologies (e.g., custom, semi-custom, gate-array, standard-cell, FPGA), as well as for newly developed and emerging IC design methodologies. The present invention also provides a method for accurately characterizing the overall IC design based on creating and accurately characterizing large regions of the design at the transistor-level.
The present teachings include a method for improving the utilization of existing cells in a standard-cell library, minimizing the number of new standard-cells created to implement a digital circuit when on-the-fly creation of standard cells is allowed, and improving the characterization of standard-cells given their context-of-use or environment. Also provided is an accurate method for characterizing the entire design based on creating and accurately characterizing groups of standard-cells at the transistor-level.
In accordance with the present teachings, the method and system of minimizing the number of unique standard cells required to implement the digital circuit is referred to herein as uniquification. As used herein, characterization refers to a process by which a logic cell is analyzed extensively for its characteristic properties, such as pin-to-pin rise/fall times and power consumption. The characterization aspects of the present teachings are applicable over a wide variety of environmental conditions, such as the various semi-conductor process nodes at which the cell can be fabricated.
Conventional standard cell-based design flows involve the creation of a fixed set of standard-cells (called a library), and their use (instantiation) in implementing multiple designs. Recent efforts to improve design performance have resulted in a new design flow in which the generation of cells with entirely new functionality is performed on-the-fly, i.e., in a dynamic manner. In this context, the following considerations are relevant: minimization of the number of unique new standard-cells that need to be generated; the reduction in the resources required for characterizing the new standard-cells; and the accuracy of results achieved by the characterization process.
In contrast to other techniques related to the uniquification problem, the present teachings disclose a method and system for identifying matching cells based on at least the following set of criteria: target functionality of the required cell, considering potential permutations and complementation of inputs; and target constraints on the properties of the required cell such as pin-to-pin rise/fall times, input/output capacitances, switching capacitances, power, foot-prints, noise margins, pin-placement, etc.
In contrast to other characterization techniques, the present invention provides effective utilization of restrictions/information regarding the operating environment (i.e., context-of-use) of the standard-cell(s) being characterized. Such restrictions/information may be derived from context-specific knowledge, as is true for the new design flows that generate cells on-the-fly, where the points of instantiation of any cell in a design are known. This knowledge is used to reduce the resources required for characterizing new standard-cells and for improving the accuracy of the characterization process. In addition to the design environment knowledge, constraints utilized by the present invention may come from other data concerning the cell and its intended use.
The above and other objects, advantages, and benefits of the present invention will be understood by reference to following detailed description and appended sheets of drawings.